• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
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    • 专利摘要:
    Analog-digital converter with value balance module. Which achieves a high conversion speed and a high resolution in terms of the number of bits, and which comprises: a value balance module (1); a module for generating rail voltages (3), connected to the module for balancing values (1); a bit generation module (2), connected to the output of the value balance module (1); and a generator module (4) of reference voltage fractions (Vref), connected to the input of the value balance module (1) and to the input of the bit generation module (2) . (Machine-translation by Google Translate, not legally binding)
    公开号:ES2777999A1
    申请号:ES202030255
    申请日:2020-03-30
    公开日:2020-08-06
    发明作者:López Armando Segui；Zanón Enrique Berjano
    申请人:Universidad Politecnica de Valencia；
    IPC主号:
    专利说明:

    [0004] OBJECT OF THE INVENTION
    [0006] The object of the invention is an analog-digital converter with a value balance module, which achieves a high conversion speed and a high resolution in terms of the number of bits.
    [0008] BACKGROUND OF THE INVENTION
    [0010] Analog-digital converters (CAD) are used in many applications, since most of the signals captured by electronic sensors are analog, and in many applications these signals must be processed by digital systems, which is why their analog signal conversion is necessary. to digital signal. Digital signals are characterized by their resolution, which is measured by the number of bits. The higher the number of bits, the higher resolution the CAD has.
    [0012] There are different types of CAD, among which the flash, successive approximation or sigma-delta converters stand out. Flash-type converters are the fastest converters. As a drawback, its implementation requires a very high number of comparator circuits. Specifically, they need 2n - 1 comparators, where n is the number of resolution bits. This causes flash-type converters to be limited to 10 bits of resolution, as it is difficult to make converters with more than 1024 internal comparators (210 - 1). In contrast, successive approximation or sigma-delta converters require far fewer internal components, but are much slower to convert.
    [0014] In the state of the art, document US2019268557A1 refers to an analog-digital converter device that uses operational amplifiers and resistors, with sequential comparators in series connected stages, with a high conversion speed and low energy consumption.
    [0016] For its part, document JPH0522139A describes an analog-to-digital converter device with a high conversion speed that distributes the inputs between groups of comparators maintaining a constant input impedance and reducing the length of the conductive paths, which reduces the space that the circuit occupies and the number of comparators.
    [0018] DESCRIPTION OF THE INVENTION
    [0020] The analog-digital converter of the present invention is divided into four modules: a value balance module, a rail voltage generation module, a bit generation module and a reference voltage fraction generation module.
    [0022] The analog-digital converter of the present invention, in its implementation with n- bit resolution, comprises:
    [0023] - a stock balance module, comprising n-1 stock balance comparators, connected in series,
    [0024] - a rail voltage generation module, comprising 2 (n-1) rail voltage generators, each one being connected to a value balance comparator, - a bit generation module, comprising n generation comparators bits connected to the stock balancing module, and
    [0025] - a reference voltage fraction generator module ( V rê), comprising n reference voltage fraction generators, and which supply the value balance comparators and the bit generation comparators.
    [0027] Each of the modules and the relationships between them are described below.
    [0029] Both the bit generation module and the rail voltage module comprise a series of comparators, which have been called value balance comparators in one case and bit generation comparators in another, to facilitate their differentiation.
    [0031] In any case, all analog comparators comprise two analog inputs (a positive analog input (F +) and a negative analog input (y -)) and an output (y0). Furthermore, they comprise a positive supply terminal (ycc +) and a negative supply terminal (ycc-).
    [0032] In general, when the positive input ( V + ) has a higher voltage than the voltage at the negative input ( y - ) , the output ( V0) takes a high value. If the positive input ( V + ) has a lower voltage than that of the negative input ( y - ) , the output ( V0) takes a low value.
    [0034] If a rail-to-rail op-amp is used as the comparator, the high and low values correspond almost exactly to the values that are placed across the positive ( and cc +) and negative ( and cc_) power terminals. That is, when the positive input ( y + ) has a higher voltage than the negative input ( y _ ) , the output ( V0) will have the same value as the positive power terminal ( and cc +), while When the positive input ( y + ) has a lower voltage than the voltage at the negative input (y _ ) , the output ( V0) has the same value as the negative power terminal ( y cc_).
    [0036] Next, and for simplicity, the operation of an analog-digital converter with a 4-bit value balance circuit is described, that is, with n = 4 , being the extension to the case of a greater number of bits (8, 10, 12, etc.) extrapolated from the description that follows.
    [0038] Specifically, in the case of n = 4 , the stock balance module will comprise n - 1 = 3 stock balance comparators, the rail voltage generation module will include 2 ( n - 1) = 6 rail voltage generators , the bit generation module comprises n = 4 bit generation comparators and n = 4 reference voltage fraction generators ( Vref).
    [0040] An analog signal to be digitized ( y 00) is input to the negative input ( y _) of a first balance comparator of the balance module. A voltage equal to half a reference voltage ( Vref ) is introduced through the positive input ( y +). The voltage and re / is the maximum voltage to digitize, also called full scale voltage (FS). It is a very accurate and stable internal voltage value.
    [0042] If the input voltage y 00 is higher than y re / / 2 , the output V01 of the first value balance comparator takes the value of the voltage at the negative power supply terminal ( y cc_). On the contrary, if the input voltage V00 is lower than Vrej / 2 , the output V01 of the first value balance comparator takes the value of the voltage at the positive supply terminal ( and cc +), that is, V01 = y oo .
    [0043] The voltage at the negative supply terminal ( Vcc_) is equal to V00 - Vref l 2 and is obtained from the rail voltage generation module, which is described later in detail.
    [0045] In this first comparison of the first value balance comparator, it is analyzed whether the input voltage V00 is greater or less than half the reference voltage ( V rê), which conditions the value of its output V01.
    [0047] On the other hand, the bit generation module makes it possible to generate the second most significant bit from the V01 output , and the MSB from V00.
    [0049] The first stock balance comparator obtains an analog signal at its output V01 which is introduced into a second stock balance comparator, specifically at the negative input V_. At its positive input V + a voltage equal to one fourth of the reference voltage ( Vref) is introduced. Therefore, the negative input voltage V_ is a function of the output voltage of the first value balance comparator.
    [0051] If the voltage at the negative input (V01) is greater than Fre / | 4, the voltage at the output of the second value balance comparator (V02) takes the value of the voltage at the negative power supply terminal ( Vcc_), which in this case it is V01 - Vref l4. On the contrary, if the voltage V01 is lower than Vrej l4, the output ( V02) takes the value of the voltage at the positive power supply terminal, that is, V02 = V01.
    [0053] The voltage V01 - V refl4 of the negative power supply terminal ( Vcc_) is obtained from the rail voltage generation module.
    [0055] In this second comparison of the second value balance comparator, it is analyzed whether the output voltage of the first value balance comparator (V01) is greater or less than a quarter of the reference voltage Vreíl4, which determines the value of its output V02. The bit generation module will generate the value of the third most significant bit from the V02 output .
    [0057] Similarly, a third stock balance comparator will be connected.
    [0059] In summary, the operation of the stock balance module is such that when the negative input (V_) of each stock balance comparator has an analog weight greater than the corresponding fraction of Vref ( Vref / 2 in the first, and re / / 4 in the second, etc.), the voltage at the output ( V 0) will be the difference between the negative input ( and -) and said fraction.
    [0061] This output voltage ( V 0) enters the following value balance comparator, and also the bit generation module, which generates a logic high level ("1"). In the event that the negative input ( and -) does not have enough weight (that is, it is less than the corresponding fraction of y re /), the output will be directly the same value as the input. This output voltage will enter the next value balance comparator, and also in the bit generation module, which will generate a low logic level ("0").
    [0063] The bit generation module comprises bit generation comparators, in this case four. The voltage at its positive input is y 00 in the case of the first comparator, and 01 in the second, and 02 in the third, and so on. The voltage at its negative input is Vref / 2 in the first, and re / / 4 in the second, and re / / 8 in the third, and so on. Bit generating comparators provide a high logic level when the voltage at its positive input ( y +) is greater than the voltage at its negative input ( y -), and a low logic level when the voltage at its positive input ( and +) is less than the voltage at its negative input ( and -).
    [0065] The high logic level corresponds to the voltage introduced by its positive supply terminal ( and cc +) and the low logic level corresponds to the voltage introduced by its negative supply terminal ( and cc-). For example, when the bit generation comparators are supplied with a voltage of 5V at their positive supply terminal ( and cc +) and 0V at the negative supply terminal ( and cc-), the high level will be 5 V and the level under 0 V.
    [0067] The analog-digital converter with a balancing module described has the advantages of having a high conversion speed, from the range of flash-type CAD converters, but with a smaller number of comparators. Therefore, a CAD converter is implemented with a number of bits of resolution greater than 8, maintaining high conversion speeds.
    [0068] DESCRIPTION OF THE FIGURES
    [0070] To complement the description that is being made and in order to help a better understanding of the characteristics of the invention, according to a preferred example of a practical embodiment thereof, a set of figures is attached as an integral part of said description. where, for illustrative and non-limiting purposes, the following has been represented:
    [0072] Figure 1.- Shows a diagram of an analog comparator with two analog inputs ( V + and V -), one output ( V 0) and two power terminals ( Vcc + and Vcc-).
    [0074] Figure 2.- Shows a diagram of the first stock balance comparator.
    [0076] Figure 3.- shows a diagram of the second stock balance comparator.
    [0078] Figure 4.- Shows a diagram of the value balance module for the case of four-bit resolution.
    [0080] Figure 5.- Shows a diagram of the connection between the value balance module and the bit generation module, for the case of four-bit resolution.
    [0082] Figure 6.- Shows a diagram of the operation of the first stage in the case of input voltage Vin = 3.13 V.
    [0084] Figure 7.- Shows an operating diagram of the second stage in the case of input voltage Vin = 3.13 V.
    [0086] Figure 8.- Shows an operating diagram of the third stage in the case of input voltage Vin = 3.13 V.
    [0088] Figure 9.- Shows an operating diagram of the first stage in the case of input voltage Vin = 1.563 V.
    [0090] Figure 10.- Shows an operating diagram of the second stage in the case of input voltage Vin = 1.563 V.
    [0091] Figure 11.- Shows an operating diagram of the third stage in the case of input voltage Vin = 1.563 V.
    [0093] Figure 12.- Shows the stock balance module in one aspect of the invention.
    [0095] Figure 13.- Shows a diagram of the rail voltage generation module in one aspect of the invention.
    [0097] Figure 14.- Shows four examples of reference voltage fraction generators in one aspect of the invention.
    [0099] Figure 15.- Shows a general diagram of a 4-bit resolution analog-digital converter, with the value balance module (upper), the rail voltage integration module (squares in the center), and the generation module of bits (lower), in which the dashed arrows represent the slowest path that the signal makes when being processed by each module.
    [0101] Figure 16.- Shows the state of the art of CAD converters in terms of number of bits (ordinate axis) and conversion speed (abscissa axis), the line in bold being the CAD converter with stock balance module.
    [0103] Figure 17.- Shows a general diagram of the 4-bit resolution analog-digital converter, with the value balance module (upper), the rail voltage integration module (squares in the center), the bit generation module (bottom), and the connections to the reference voltage fraction generator modules.
    [0105] Figure 18.- Shows a diagram of the n-bit analog-digital converter.
    [0107] PREFERRED EMBODIMENT OF THE INVENTION
    [0109] A series of aspects of the analog-digital converter (60) with a value balance module, object of the present invention, are described below with the aid of Figures 1 to 18.
    [0111] The analog-digital converter (60) has a resolution of n bits, is represented schematically in figure 17 (for the case of n = 4), and comprises:
    [0112] - a stock balance module (1), comprising n-1 stock balance comparators (101, 102, 103) connected in series, represented in Figures 2 and 3 individually, and connected in Figure 4,
    [0113] - a rail voltage generation module (3), represented in figure 13, comprising 2 (n-1) rail voltage generators (301, 302, 303), connected to the balance value comparators (101 , 102, 103),
    [0114] - a bit generation module (2), comprising n bit generation comparators (201, 202, 203, 204), represented in figure 5, connected to the value balance module (1), and
    [0115] - a generator module (4) of reference voltage fractions ( V rê), represented in figure 14, comprising n fraction generators (41, 42, 43, 44), connected to the value balance module (1) and to the bit generation module (2).
    [0117] In addition, figure 1 represents a generic analog comparator, which is the basic element for the implementation of the value balance module (1) and the bit generation module (2), which have been called balance comparators. values in one case (101, 102, 103) and bit generation comparators (201, 202, 203, 204) in another, to facilitate their differentiation.
    [0119] In any case, all comparators, as represented in figure 1, comprise two analog inputs (a positive analog input ( y +) and a negative analog input ( y -) and an output ( y 0). In addition, they comprise a positive supply terminal ( and cc +) and a negative supply terminal ( and cc-).
    [0121] Its operation is such that when the positive input ( y + ) has a higher voltage than the voltage at the negative input ( y - ) , the output ( y 0 ) takes a high value. If the positive input ( y + ) has a lower voltage than the negative input ( y - ) , the output ( V0) takes a low value.
    [0123] Next, the operation of the analog-digital converter (60) object of the invention is explained, in the case of an analog-digital converter (60) with resolution of n = 4 bits with reference voltage and re / = 5 V. Specifically , the operation of each of the modules will be explained for two examples of input voltage: 3.13 V and 1.563 V.
    [0125] In the case of input voltage 3.13 V, in a first stage represented in figure 6, the input voltage y 00, which is introduced into the module through the negative input ( y -) of a first value balance comparator (101) would be V 00 = 3.13 V. Since 3.13 V is greater than
    [0126] (101) there is a voltage V 01 = V 00 - ( - y ^ ) = 0.63 V , which passes to the negative input ( y -) of a second value balance comparator (102), as shown in Figure 6. Simultaneously, given that 3.13 V is greater than = 2.5 y , and that it is the voltage that is introduced through the positive input ( y +) of the first bit generation comparator (201), the bit will take a value of 5 V, that is, a high logic value (this is Bit 0, MSB, according to figure 5).
    [0128] In a second stage, represented schematically in figure 7, V 01 = 0.63 V, which is introduced through the negative input ( y -) of the second value balance comparator (102). At this stage, since 0.63 V is less than ^ ^ = 1.25 V the output ( y 0) of the second value balance comparator (102) will have a value equal to that of the negative input ( y -), that is, V 02 = 0.63y . This voltage value will be the one that enters a third value balance comparator (103). Simultaneously, since V 01 = 0.63 V, it is less than ^ £ = 1.25 y . and that is the voltage that is introduced by the positive input ( y +) of the second bit generation comparator (202), the bit generation module (2) generates in this position a low value bit (this is the Bit 1 according to figure 5).
    [0130] Figure 8 schematically represents the operation of a third stage, which in this specific example is the last stage. The input voltage at the negative input ( y -) of the third value balance comparator (103) is V 02 = 0.63 V. When compared with the value of the positive input ( y +), which in this case has a value of
    [0132] Finally, the bit generation module (2) compares the output value ( y 03) of the third value balance comparator (103) with
    [0133] Therefore, in this exemplary embodiment, the final result of the analog-digital conversion, generated in the bit generation module (2), is 1010.
    [0135] In the case that the input voltage is 1,563 V, in the first stage, represented in figure 9, the input voltage V00, which is introduced into the module through the negative input (and -) of the first comparator of balance of values (101), it would be V00 = 1.563 y.
    [0137] Since 1.563 V is in this case less than
    [0139] Simultaneously, since 1.563 V is less than ^ p = 2.5 V and that is the voltage that is introduced by the positive input (y +) of the first bit generation comparator (201), the most significant bit (MSB) will take a value 0 V, that is, a low logic value.
    [0141] In the second stage, represented schematically in figure 10, V01 = 1563 V, which is introduced by the negative input (y -) of the second balance value comparator (102).
    [0143] At this stage, since 1.563 V is greater than = 1.25 y, and that is the value introduced by the negative input (y -) of the second balance value comparator (102), the output (y0) of the second balance comparator value (102) will have a value y01 - - ^ £ = o.313y. This voltage value will be the one that enters a third value balance comparator (103).
    [0145] Simultaneously, the bit generation module (2) generates a high value bit, since 1.563 V is greater than = 1.25 y, and that is the value introduced by the positive input (y +) of the second bit generation comparator ( 202).
    [0147] In figure 11 the operation of the third stage is schematically represented. The input voltage at the negative input (y -) of the third value balance comparator (103) is y02 = 0.313 y. When compared with the value of the positive input (y +), that in this If it has a value of 8 = 0.625 V, it causes the output ( V0) of the third value balance comparator (103) to be equal to ^> 3 = ^ 02 = 0.313 V.
    [0148] Simultaneously, since 0.313 V is less than = 0.625 V, and that is the value introduced by the positive input (V +) of the third bit generation comparator (203), the bit generation module (2) generates in this position a low value bit.
    [0150] Finally, the bit generation module (2) compares the output value ( V0) of the third value balance comparator (103) with = 0.3125 V, and generates the least significant bit, which is 1 in this case, since 0.313 is greater than 0.3125 V.
    [0152] Therefore, in this exemplary embodiment, the final result of the analog-digital conversion, generated by the bit generation module (2), is 0101.
    [0154] In figure 12, a possible implementation is shown for each of the stock balance comparators (101, 102, 103). It is shown specifically for the first stock balance comparator (102). It comprises an operational amplifier (7) supplied symmetrically with ± 5 V at its positive and negative supply terminals (Vcc +, ycc_), respectively. Connected to the output of the operational amplifier (7), there is a complementary pair of transistors (8), of the MOSFETs type, one pMOS and the other nMOS.
    [0156] When V00 at the positive input (V +) is greater than yre // 2 of the negative input (y -), the op amp output saturates positive (+ Vsat), causing the pMOS to be in a non-conducting state, and that the nMOS is conducting, which allows to have the voltage y00 - yre // 2 at y01.
    [0158] On the contrary, if y00 is less than yre // 2, the operational output saturates negatively (-y Sat), causing the nMOS to be in the non-conducting state, and the pMOS to be in the conducting state, which allows to have the voltage y00 in V01.
    [0160] For its part, as shown in Figure 5, the bit generation module (2) in the previous examples, comprises n analog comparators (201, 202, 203, 204).
    [0162] In addition, the rail voltage generation module (3) is responsible for providing the voltages of the negative power terminals (Vcc_) to the comparators of balance sheet (101, 102, 103). The positive supply terminal voltages ( V dc +) are obtained directly from the positive input voltage (F +) of each value balance comparator (101, 102, 103). Figure 13 shows the general structure to achieve negative supply terminal voltages (Vcc-). Each of these voltages (Vcc-) is the difference between the positive input voltage (F +) of the balance value comparators (101, 102, 103) and a fraction of the reference voltage.
    [0164] The operation is as follows. Vref is the scale reference voltage of the analog-digital converter (60) and V00 is the analog input to be digitized. Taking as an example the case of an analog-digital converter (60) with n = 4 bits, like the one in figure 5, the voltage of the negative supply terminal (Vcc-) of the first value balance comparator (101) is achieved by a first inverting amplifier with a supply resistance of value R / 2 (301), followed by a weighted inverting adder (302) that provides an output of value V00 - Vref / 2.
    [0166] Similarly, the negative supply terminal voltage (Vcc-) of the second value balance comparator (102) is obtained by a first inverting amplifier (301) with a feedback resistor of value R / 4, followed by an adder weighted inverter (302) in which the output (V0) of the first stock balance comparator (101) is directly input. This achieves an output voltage of the value V01 - Vref / 4, and so on.
    [0168] In order to achieve voltages equivalent to fractions of the reference voltage ( V rê), in one aspect of the invention, the generation module (4) of reference voltage fractions (Fre /) is used, comprising n operational amplifiers. Figure 14 shows four resistive dividers followed by op-amp-based buffer circuits (41, 42, 43, 44). The first generates a voltage Vrej / 2, the second Vrej / 4, and so on.
    [0170] In summary, as shown in figure 18, the implementation of the analog-digital converter (60) with a value balance module with n bits of resolution comprises a total of n - 1 value balance comparators (101, 102 , 103) for the value balance module (1), n bit generation comparators (201, 202, 203, 204) for the bit generation module (2), 2 (n-1) operational amplifiers (301 , 302) for the rail voltage generation module (3), and n generation operational amplifiers (41, 42, 43, 44) for the generator module (4) of reference voltage fractions ( V rê). In total, 2n - 1 comparators and 3 n - 2 op amps.
    [0172] If we consider that the comparators could be based on rail-to-rail operational amplifiers, the total number of amplifiers would be 5 n - 3. This implies that for an 8-bit analog-digital converter (60) only 37 operational amplifiers are required, compared to the 256 which requires a flash CAD converter.
    [0174] The difference is even greater for the case of a 10-bit converter, where only a flash-type CAD converter needs 1024 operational amplifiers, while, with an analog-digital converter (60) with a value balance module, such as that of For the present invention, only 47 op amps are needed.
    [0176] The critical parameter when comparing different architectures of analog-digital converters is the conversion time, which would be the time that the converter requires to carry out a complete conversion.
    [0178] Its inverse is the conversion speed, which is measured in mega samples per second (MS / s). In order to estimate the conversion time of the analog-digital converter (60) with the balance of values circuit, we take as an example the case of a converter with n = 4 bits, as shown in figure 5. Figure 15 shows the same electrical diagram highlighting with broken arrows the slowest path in the processing of the input signal V00. Each arrow represents the processing by an operational amplifier of the rail voltage generator module (3) or by a comparator of the value balance module (1) or the bit generation module (2).
    [0180] It is assumed that both the reference voltage (Fre /) and its different fractions obtained by the rail voltage generation module (3), shown in figure 13, are available as soon as the converter is powered, so they do not contribute to the analog-digital conversion time.
    [0182] First, the V00 signal must pass through the rail voltage generation module (3) to be able to generate a voltage V00 - y re // 2. To be able to create this rail voltage, a delay time tA0 associated with the second operational amplifier must be expected. (302) of the rail voltage generation module (3) shown in figure 13 (the first operational amplifier (9) should not be taken into account in this analysis).
    [0184] Once the voltage V00 - - ^ - is available, we will have to wait for a delay time tc associated with the first value balance comparator (101). From there, the analysis is repeated until reaching the V0 output of the third stock balance comparator (103). Once there, it only remains to add the time tc associated with the fourth bit generation comparator (204), which generates the least significant bit (LSB). All in all, it follows that the conversion time of an entire analog-digital converter (60) with an n-bit value balance module is n ■ ( tA0 + tc) + tc.
    [0186] The delay time tc associated with a rail-to-rail comparator can be as little as 4.5 ns. For the operational amplifiers we have delay times tA0 of 5 ns. With these guide values it is possible to estimate the conversion time and the conversion speed as a function of the number of bits.
    [0188] Figure 16 shows the relative position that the analog-digital converter (60) occupies with a value balance module in relation to other types of converters already established such as a flash-type CAD converter (50), a successive approximation CAD converter (51 ), or a sigma-delta CAD converter (52).
    [0190] It is a scheme in which the analog-digital converter (60) of the present invention is compared with the current state of the art, representing the conversion speed (MS / s) on the abscissa axis of the graph and in the ordinate axis the number of bits of the converter. As can be seen in figure 16, the results confirm that the analog-digital converter (60) with a value balance module has advantages in terms of resolution and speed, especially when the number of bits is high (24).
    权利要求:
    Claims (3)
    [1]
    1. - Analog-digital converter (60) with value balance module, with n-bit resolution, comprising:
    - a stock balance module (1), comprising n-1 stock balance comparators (101, 102, 103) with a positive input ( y +), a negative input ( and -), an output ( V0) and positive and negative supply terminals ( VCC +, VCC-), the negative input ( and -) of a first value balance comparator (101) being supplied with an input voltage and 00, and the output ( V0 ) of each balance sheet comparator (101, 102, 103) n-1 to the negative input ( y -) of the next balance sheet comparator (101, 102, 103) n,
    - a rail voltage generation module (3), comprising 2 (n-1) rail voltage generators (301, 302, 303), comprising an input supplied by a reference voltage Vref and a supply output to the negative supply terminal ( Vcc-) of the value balance comparators (101, 102, 103), with a voltage of value Von - Vreí¡2n + 1 ,
    - a bit generation module (2), comprising n bit generation comparators (201, 202, 203, 204), each one being supplied at its positive input ( and +) by the voltage V0n-1 of the comparators balance of values (101, 102, 103), and generating a bit at its output V0 , generating the highest bit in a first bit generation comparator (201), and an n bit generation comparator the bit of lower weight, and
    - a generator module (4) of reference voltage fractions ( Vref ), comprising n fraction generators (41, 42, 43, 44) that supply the n-1 voltage comparators with a voltage Vref / 2 n + 1 balance of values (101, 102, 103) by their respective positive inputs ( and +) and to the n bit generation comparators (201, 202, 203, 204) by their respective negative inputs ( and -).
    [2]
    2. - The analog-digital converter (60) of claim 1, in which the value balance comparators (101, 102, 103) comprise an operational amplifier (7) fed symmetrically at its positive power terminals and negative ( VCC +, VCC-) respectively, and transistors (8) connected to the output of an operational amplifier (7).
    [3]
    3.- The analog-digital converter (60) of claim 1, wherein the rail voltage generators (301, 302, 303) comprise a first inverting amplifier (9) with a supply resistance of value R / 2n +1 (10), followed by a weighted inverting adder (11) that provides an output value Von - Vreí / 2 n + 1 .
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    同族专利:
    公开号 | 公开日
    ES2777999B2|2020-12-16|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20040263366A1|2003-06-30|2004-12-30|Renesas Technology Corp.|Semiconductor integrated circuit|
    US20130162456A1|2011-12-23|2013-06-27|Industrial Technology Research Institute|Analog to digital converting apparatus and method thereof|
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